Previous recent disk drive architectures have included embedded programmed digital micro controllers for controlling various functions of the disk drive, including, for example, tasks such as head positioning, spindle motor speed regulation, read channel adjustments for zoned data recording, and data block transfer and supervision in response to commands received from a host computing system. These prior designs have typically included a large data cache memory array for temporary storage of multiple data blocks in transit between the disk data storage surface and the host computing system. Separately, the embedded microcontroller has typically required internal and external read only program memory (ROM) for storage and retrieval of control program routines, and scratchpad random access memory (RAM) for program variables and tables, etc.
When disk drives were physically larger, and commanded higher prices, designs providing several separate memory chips for program memory and scratchpad access memory, separate and apart of the data block transfer buffer memory, were feasible and then deemed to be cost effective. Two marked trends have brought into focus the drawbacks of these prior approaches. One trend is that disk drives are becoming physically much smaller; and very small form factors in the 2.5" disk diameter and the 1.8" disk diameter size ranges are increasingly in use. Small disk drives require size-reduced electronics circuit boards. In turn, the electronics chips must support multiple functions, and the number of electronics chips must be reduced to a bare minimum. Another requirement is reduction of power consumption in these very small disk drives. The other trend is massive cost reductions presently being required by manufacturers and integrators of computing systems into which small hard disk drives are being installed and used. Separate program and random access memory arrays add significant costs to, and require precious board space on, the electronics printed circuit board portion of the hard disk drive assembly.
The concept of storing control program routines on a data surface of a hard disk drive and calling them for execution as needed is not new. Commonly assigned U.S. Pat. No. 4,396,959 to Harrison et al. (later U.S. Reissue Pat. No. 32,075) describes an arrangement whereby diagnostics routines were stored on the disk and called by the drive's embedded microcontroller for execution as required. In commonly assigned U.S. Pat. No. 4,669,004 to Moon et al., a disk drive was described in which the disk stack had seven cylinder locations reserved for system software. These locations included a dynamic media defect map which was called by the embedded microcontroller as part of its media defect management control routine. U.S. Pat. No. 4,746,998 to Robinson et al. describes a disk drive in which a media defect list supplied by the drive manufacturer was stored on outer tracks of the storage disk. The defect list was then merged with a user-supplied defect list during formatting and used to flag and bypass defective data sector locations. During initialization of the drive, the merged defect list was loaded into a section of memory directly accessible by the embedded drive microcontroller, so that it may take defect locations into account during track seeking operations. Commonly assigned U.S. Pat. No. 5,084,791 to Thanos, et al. describes a disk drive architecture in which the embedded microcontroller was provided with internal and external RAM and ROM. There was also an indirect data path for the microcontroller to the block buffer memory so that error correction operations could be performed on data blocks in transit before delivery to the host computer.
An example of this indirect data path is provided in the FIG. 1 illustration of prior art. In FIG. 1 within a hard disk drive architecture a drive microprocessor was connected to a microcontroller interface. The interface was within a drive electronics chip including a memory controller. The memory controller generated addresses and supervised data block transfers into and out of a drive cache buffer memory array, either from the disk storage surface, or from a host interface circuit. When the microprocessor desired to write data into the cache buffer array in accordance with a data move instruction, the microprocessor transferred from its accumulator a starting address location into the address register and then a data byte into the data register. When the data byte was placed into the data register, the memory controller then caused the data to be written to the address pointed to in the cache buffer memory array at a subsequent time in the memory access cycle, usually within one or several microseconds after the data byte was stored into the data register. During this delay interval, the microprocessor had to enter a delay, as by executing "no-operation" loops until passage of the maximum time necessary to assure that the memory controller had transferred the byte to the cache buffer array. After this delay time for data transfer to the memory elapsed, the microprocessor then wrote a second byte into the data register, and thereupon an incrementing function (noted as "+1" in FIG. 1) automatically incremented the address register value by one. This indirect data transfer procedure was then repeated, with the microprocessor waiting for the delay time needed to transfer the second byte, before sending a third byte, etc. This "double-clutching" procedure through the data register then continued until all of the data bytes of a string were sent to the buffer memory array.
During reading operations, the microprocessor would load a starting address into the address register, and then wait for the delay time needed by the memory controller in fetching the byte from the cache buffer memory array into the data register. The act of reading the data from the register by the microprocessor then caused the address incrementer to increment the address by one, and the next byte was fetched and temporarily stored in the data register until it was accessed by the drive microprocessor. This process continued until the block of data bytes desired to be read by the microprocessor was fetched and transferred via the data register. The act of accessing the data register, whether for read or write, were carried out by the microprocessor via a "move" instruction. These external data transfer operations were instruction-intensive, and the external cache buffer memory array did not appear as address space to the microprocessor. Also, transfers were restricted to and from the accumulator of the microprocessor, and instructions were not capable of being fetched from the external array into the instruction register and then executed.
As illustrated by the foregoing example, the use of a single memory chip to store data blocks in transit as well as control program routines, variables and tables has presented a number of difficult problems for the disk drive designer. In order for the embedded disk drive controller to execute its control program routines from the single memory, the memory controller must have sufficient reserve bandwidth to allocate direct access to the microcontroller in order to achieve reasonable code execution performance. The block buffer memory must appear to the microcontroller to be directly addressable within the micro controller's limited direct address space. Synchronization of the microcontroller and the block buffer controller is required when other users need to have direct access to the buffer at the same instant as may be needed by the microcontroller. At least three memory segments must be defined at all times: a first segment for data blocks in transit; a second segment for the current control program routine being executed by the microcontroller, and a third segment for scratchpad memory for variables and tables.
The present invention provides a solution to the hitherto unsolved problems associated with use of a shared memory for both data block and control program storage within a disk drive.